Hi everyone,
I am trying to optimize my data in FPGA and reduce the data movement between off-chip memory and FPGA. one of the possible techniques is the data reuse methodology. I need a reference, lecture or tutorial to learn about the spatial and temporal reuse techniques. I appreciate any help or guidance from you in advance.
I hope the following books help you:
1. Joseph P. Elm "Designing for Reuse of Configurable Logic" 2005
2. Michael Keating "Reuse Methodology Manual: For System-on-a-Chip Designs" third edition
Hi everyone,
Hope this paper helps "Configuration Prefetching and Reuse for Preemptive Hardware Multitasking on Partially Reconfigurable FPGAs" found in http://ieeexplore.ieee.org/document/7459551/ check also the references. This paper deals with trying to reduce the reconfiguration time of partial regions when the configuration bits of partial regions are outside the FPGA, via two techniques: prefetch and reuse. You may extend the concept to multiple FPGAs.
Dear Behdad Jamadi ,
I think this is an important question regarding the system design and implementation using FPGAs. The FPFAs contain what is called block ram that can be used as internal memory on the chip. IN case of Memory intensive applications one may an extremal memory. Sure the external memory may take relatively long time to access compared to the block ram which can be made to neighbor the processing block. So, the block ram may function as a cash memory for the local processors. As said before only the data which would be accessed much fewer times can be sent to the off chip memory. It is similar to the cash memory and external memory of the microprocessors.
Best wishes
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