In testing some full adders under same test-bed(discussed in link below)
https://www.researchgate.net/post/What_is_a_proper_test-bed_for_full_adders_in_VLSI_designs?_tpcectx=qa_overview_asked&_trid=40QOTQdDYM80jUqe2A85D5IW_
a) After I changed the frequency of inputs in transient analysis, load capacitance of full adder didnot change! But I didn't think so. Is it typical?
b) After I tested different full adders under the same test-bed (with the same Input/Output buffers size), The load capacitance of different full adders became different (not so much)! Is this typical too!!?
hey there!
It could be Depend on the frequency characteristics ( like energy iteration etc.) and what elements it affecting on. and as you mentioned it's kind of weird to see no change in capacitance load, so there would be two kinds of theories here:
1- there is no relation between frequency and this special kind of adder. (it's very odd and strange but sometimes simulators getting mad!)
2- the variation in load is so small that the simulator can't afford that or can't be distinguished by this simulator/adder design.
what is in my mind is about recheck all parameters(related to capacity first then if it still not working go on the rechecking all! too much work!) there should be some points that are not work to gather properly.
you can do some tricks here, get all documentary results in a file and analyze that in new simulation platforms like Matlab, because most related but marginal parameters in this simulation can be done in this programming language.
it was all I knew but the most important thing here is this :
"We can't solve problems by using the same kind of thinking we used when we created them."
I hope they work for you.
be happy solving the problem.
Regards
Yasin
Dear Maryam,
From the conceptual point of view every mos transistor as a switch in the circuit has an input CGS capacitance and a an on-resistance. So, if we build a circuit using this transistor e.g. an inverter loaded by a a load capacitor CL it will react on the abrupt input voltage changes by a slowing slowing the change of the output voltage from the high to low and from the low to high. Which means that the output voltage will not change instantly but will take time to charge and discharge the the output load capacitor. These slow transition are characterized by the propagation delay time where the output swing changes to 50 percent of its steady state value and this is determined by the the time constant ron x CL where ron is the on resistance of the transistor.
So, increasing the input pulse rate by increasing its frequency will lead to shrink the steady state time of the pulses which will be ultimately zero and the output waveform will appear triangular. This will be the maximum input possible bit rate, since the logic will not be correctly evaluated because there is no static logic level.
In the detailed equivalent circuit of the mos devices it is assumed that there equivalent capacitors are independent of frequency.
Best wishes
Yasin Asadi
Thanks, Using Matlab can be a good idea!
Abdelhalim Zekry
Thank you,
About question a) : If the input frequency of circuit does not effect to CL, there is an assumption for me:
When in literatures at the time of testing the circuits, the larger CL is determined for the larger frequency, so I should increase the W and L of buffers(in test-bed with two input buffers and one output buffer) to get a larger CL by myself and increasing in the frequency does not effect to CL and increasing in the CL value is besause of deacreasing in the charge/discharge time of CL (when we increase frequency).
Are my thoughts correct?
About question b) :
The point is that in literatures there is one value for the load capacitance to test different circuits under a test-bed, So if the CL value depends on the structure of Circuit Under Test and we will have different CL values at the outputs of various CUTs, so Should we change the buffers size for every circuit under test-bed to get a same value of CL?
Really i answered your question indirectly in the first comment. Assume you have a circuit under test and you want to determine its speed of operation which is the highest clock speed of the circuit. This speed for sure depends not only on the core of the circuit which perform the operations but depend also to large extent on the off chip load CL. If you drive CL directly from the output of the processing circuit you will slow down the operation of the circuit because the on resistance ron of the processing transistor is relatively large and so the propagation delay times will be large and the maximum operating frequency will be much less. So to speed up the the logic transitions at the output one has to add buffers characterized by their large driving capability which means that the their on resistance is much less than that of the small processing transistor.
This is common technique and there are many buffer circuits. The most important thing that the buffer must be capable to drive the CL with the required speed such that it will not limit the speed of the operation.
The driver transistors have normally larger W/L ratio to decrease their on resistance which is inversely proportional to L/W ratio. So you keep L minimum and increase the width of the transistor. Normally buffers are cascaded transistors with increased W/L ratio.
To increase the drive ability of the transistors one can use the the BICMOS technology where one utilizes bipolar transistors fro the driving purposes at the output of the circuit while using cmos transistors for the logic.
In specifying digital circuits one has to give the maximum CL that can be driven by the circuit to achieve the required speed of operation.
WISH YOU SUCCESS
Capacitance of a capacitor is a finite value, and is independent of frequency. By varying the signal frequency, we can only alter its reactance. If the capacitance is high, more current should be delivered to make it charged. Which means R should be low, so that charging time constant RC becomes low. If time constant is low, you get better speed with the circuit.
- Badges
- Science topic