4 transceiver channels are required for DisplayPort. Cyclone 10 GX FPGA; also comes in the form of transceivers BANK. There are 6 transceivers on each bank. A total of 12 Transceivers come in the form of two banks. We are currently using it for 4 RX for 4 TX. We want to add another channel. But in order to make 4 transceivers, we need to get 2 transceivers from one bank and 2 transceivers from the other bank. But does this work for the Display port? Is there any limitation caused by Intel? How hard is it to add a second RX and try this?

https://www.intel.com/content/www/us/en/programmable/documentation/ufa1511788563556.html

More Murat Can Işık's questions See All
Similar questions and discussions