I saw a report of ITRS, it says:
1) 25nm gate length conventional mosfets, required for the 65nm technology node.
2) Gate length 15nm required for HP45nm technology node.
What is difference between this physical gate length and channel length and how does this gate length affects the leakage power in ultra deep sub-micron regime ?
I am asking in reference to BSIM4 models.
Channel length would be the shortest electrical distance between source and drain in a MOSFET, the gate length that of the intermediate contact above. For a normal MOSFET both are similar and shorter than the node length, which describes the smallest feature size in planar lithography.
Gate length is simply the physical gate length. Channel length is the path that links the charge carriers between the drain and the source. If you exclude the physical overlapping in the structure, gate length and channel length would be very close.
Historically, the technology node used to refer to the half pitch between two features in a circuit. Nowadays it lost its meaning and it is now used for marketing purposes rather than a real feature of a MOSFET.
Dear@Prateek,
The technology node is designated by the minimum feature size which can be fabricated in the technology. for example metal wire width, polysilicon wire width ,. etc. This includes also the nominal drawn gate length between the so source an drain under the oxide layer. The minimum real gate length is smaller because of the extending the space charge regions in the channel under the gate oxide.
Best wishes
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