The PLL is built from a voltage controlled oscillator whose free running frequency is equal to nominal frequency of the input reference voltage which in your case the 50 Hz of the reference voltage of the mains power. A phase detector which can be either a multiplying phase detector or a digital X-OR phase detector, a loop filter which is a lag lead filter. The PLL bandwidth is made very small compared to the center frequency of 50 Hz. Say 1 Hz. This PL is designed to be input recovery circuit.When the PLL locks it will make the loop frequency = fundamental frequency of the power mains frequency. It will always track it.
The role of the PLL is to track the frequency of the power grid.
You need to determine the loop parameters which is gain consatnt of oscillator and the filter parameters.
You need to read a book in the PLL such that you will be able to design it.
You may also follow the paper in the link: Article Simulation and Implementation of Grid-connected Inverters,
PLL generally comprises for the Phase detector , loop filter and the VCO in series control blocks. You can refer this paper and the modelling of PLL in Simulink and LabVIEW. https://www.researchgate.net/publication/351458196_PERFORMANCE_IMPROVEMENT_OF_FRACTIONAL_ORDER_PLL