I did that also, but the problems still remains. I am not getting the cause, why the leakage is too high, when the dielectric SiO2 is present.

What is the thickness that you have deposited?

Thanks Talha sir,  I got the point. I have deposited thick film of ZnO. 

You could try a buffer layer (on top of the SiO2). We find that Al2O3 works well - also get a better interface. Note that you then have two capacitances in series for the gate oxide.

Note also that the leakage through the gate will give you flat-band shifts in your TFTs as some electrons will be trapped in the SiO2.

It's already mentioned that you must mesa-isolate the devices or you have a very large leakage area.

In order to estimate the minimal leakage current you could deposte the Al contacts on one of your Si/SiOx substrates and measure the current between the Si and the Al contacts. This could also provide a means to compare the leakage between your standard Si/SiOx substrates and a substrate on which you deposited Al2O3 as suggested by Steve.

You should definitely prepare mesa structures to avoid cross talk and reduce leakge current as suggested by Steve and Talha.

The gate leakage current can be expressed by the simple expression I= JA, where J is the leakage current density and A is the leakage current area.

So, to reduce the I you have to reduce both to the minimum possible value.

In addition you may have short circuit by contacting ZnO to the silicon substrate. This can happen if your deposited ZnO overlaps your silicon dioxide isolating layer.

The key word is to use Mesa structures.

Best wishes