Hi there,

I came across an interesting issue while designing comparators for my ASIC. The ASIC's fundamental structure is based on the CMOS version of the legendary NE555 Timer IC.

Here's the thing:

Both comparators are realized as open-loop comparators, based on a simple differential amplifier. The THRES-Comparator (highlighted in yellow) consists of a biasing transistor, two NMOS input transistors and an active PMOS load. The TRIG-Comparator (highlighted in orange) is composed similarly, however as a version with PMOS-input transistors.

Resulting from this architecture, the devices should, as far as I understand it, have a limited input-common mode range (ICMR), that cannot be rail-to-rail in this specific case.

Now, to my knowledge, it is necessary to keep both inputs (+ and -) within a given ICMR in order to guarantee a "safe" and proper device operation. For the respective comparator reference voltages, this is set by the setup of the Timer IC. The resulting reference voltages for both comparators are 2/3 VDD and 1/3 VDD, respectively and thus predetermined. For a supply voltage of 1.8 V in 180nm-Technology this would correspond to 1.2 V for the inverting input of the THRES-comparator and 0.6 V for the non-inverting input of the TRIG-comparator.

While the differential stages can be designed to incorporate those reference voltage-levels, I am facing an issue with the "variable" input pins of both comparators (i.e. the non-inverting input for the THRES-comparator and the inverting input for the TRIG-comparator).

As I am planing to operate the whole circuit in bistable operation mode, a specific outer wiring is necessary for the circuit. Consider the picture showing the wiring of the 555 Timer in bistable mode. As it can be seen, the TRIG-comparator is driven by GND as soon as the switch S2 is closed.

I have the following questions now:

1. Is there a possibility to further extend the ICMR of the comparators based on the differential-amplifiers, while ensuring that the biasing transistor and the active load stay in saturation? For a single-supply voltage of VDD = 1.8 V I'd spend a minimum 100mV of overdrive voltage for the biasing transistor. That's the only value I can control, since the threshold voltage of the transistors is not variable.

Otherwise, I have been thinking of a workaround using a slightly higher potential below the switch in order to "artificially" realize higher potentials. The upper limit is given by the active load.

2. Generally speaking, can a comparator be operated normally with input voltages exceeding the ICMR and what is necessary in order to ensure that a comparator works correctly? Do both inputs need to be within the ICMR or is it sufficient if one of them is inside?

I appreciate all comments and help.

Thanks in advance and greetings :)

The attached pictures are taken from the listed sites and do not belong to me:

https://de.wikipedia.org/wiki/NE555

https://www.youtube.com/watch?v=i0SNb__dkYI