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Questions related from Frederik Lesniewski
It is common practice to choose minimum transistor lengths of 4-5 times the minimum process technology length for analog designs. I wondered, whether this is also true for digital circuits? I'm...
18 November 2022 4,206 2 View
Hi, I am currently designing a two-stage open loop comparator (differential amp + current sink inverter output stage) using Cadence. In order to ensure a "safe" and error-free operation of the...
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I am designing a Wien-Bridge Oscillator on an IC and wanted to realize the resistors responsible for frequency-tuning using voltage controlled MOSFET devices (as a replacement for potentiostats)....
26 July 2022 5,202 2 View
I am looking for a possibility to design a frequency-variable Wien Oscillator on an ASIC. Since I cannot use potentiometers, I am searching for an alternative. Initially, I was thinking about...
30 May 2022 6,986 4 View
Automatic Gain Control (AGC) for a Wien Bridge Oscillator can be realized using a JFET for stabilization. Does someone know of a design that uses a MOSFET instead? If so, I would be thankful if...
27 May 2022 5,301 5 View
Is a higher electrode area beneficial for electrochemical impedance spectroscopy (EIS)-experiments? And should the electrodes be placed further away from each other or is it better if they are...
30 August 2021 7,631 10 View
For my research on inkjet-printable electrodes, I want to compare the capacitance/impedance of a parallel-plate capacitor with a planar interdigitated capacitor. In order to verify my simulation...
06 August 2021 7,994 2 View
Hi there, I came across an interesting issue while designing comparators for my ASIC. The ASIC's fundamental structure is based on the CMOS version of the legendary NE555 Timer IC. Here's the...
01 January 1970 8,772 1 View
