CMOS 2NOR-gate or SR-Latch design procedure?

Frederik Lesniewski @Frederik-Lesniewski

12 October 2022 1 7K Report

I want to calculate and design a CMOS SR-Latch built from 2 cross-coupled NOR gates. However, I have problems with finding a source, that has a step-by-step explaination of the design procedure to find the adequate W/L ratios of the transistors.

Can you recommend some litereature or other sources where such a design procedure is explained in detail?

Thanks in advance :)

Sadegh Biabanifard

You can see:

https://eepower.com/technical-articles/cmos-sr-latches-and-flip-flops/#

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