Chirag Maheshwari

3 Questions 8 Answers 0 Followers

Questions related from Chirag Maheshwari

Can we specify a signal value for initial power-on reset duration in the SDC file for DC compiler?

I am working with DC compiler. My design has some sequential elements (D-FF) which reset's on negative edge of reset signal input to the design. Is there a way to tell compiler that on power-on,...

11 March 2020 4,133 6 View

Synopsys DC Compiler- Register merging options and optimization?

Hi, I am studying about how we can reduce the extra/redundant FFs from our logic using DC compiler. To understand the same, I instantiated the same design block 2 times in my top, giving it...

19 February 2020 3,595 5 View

How to practice RTL coding skill?

Is there anything like Leetcode or Hackerrank for practicing rtl design? How does most people practice problem solving for rtl design/verification?

01 January 1970 9,186 6 View