Hi Adeel Ali ,

obviously, this figure is taken from the article

http://wordpress.nmsu.edu/pfurth/files/2015/06/prog_hysteresis2010.pdf

Since the explanation in the article seems to be quite detailed to me:

If you came about the figure taken from its context, the article should be helpful;

or if you already knew the article, which part of the explanation gives you difficulty?

Joerg Fricke

Thank you so much for your reply.

I went through this paper and few others to understand 3 stage comparator with hysterisis. It's a 3 stage comparator with single output, i understood well. I wanted to clear something for another similar circuit, if you can kindly comment on that

Is the one attached in picture the same but with differential output? The connection of M3-M5 and M8-M11 confuses me a bit.

As of my understanding :

1. M1-M2 is main differential Pair.

2. M3 is a current mirror and replicate current in M5

3. M9-M11 is a common source

4. M13-M15 is an inverter.

(same story on right side.)

Is that right understanding?

Hi Adeel Ali ,

if your meaning in 2. is: M5 := M3, then 1, 2, and 4 are correct. However, I wouldn't call M9 - M11 "common source".

Assuming identical properties of the n-channel and p-channel FETs, and neglecting M1a and M2a for the moment,

- in the sub-circuit comprising M1, M3, M5, M7, and M12, the current through M12 tends to be equal to the current through M1;

- in the sub-circuit comprising M2, M4, and M10, the current through M10 tends to be equal to the current through M2.

If VINa VINb then the currents through M1 and M2 are different but the currents through M10 and M12 must be the same; consequence: VDS of M12 is either very low or near Vdd, i. e. approximately binary behavior of the stage M10 - M12.

M1a and M2a give rise to hysteresis by adding the small curent I2 either to the current in M3 or in M4 by way of positive feedback.

Joerg Fricke Thank you

I do not currently have the opportunity to delve into the specific circuit solution; so I will only give an intuitive explanation of the most general idea of ​​how hysteresis can be introduced into a switching circuit. It can be figuratively named "helping" and can be explained in such a way:

When the input voltage crosses some of the two thresholds, the element switches... and a part of its output voltage is added to the input voltage. This can be made in two ways - by decreasing the threshold or by increasing the 'circuit input voltage' (both they mean the same - increasing the 'element input voltage'). Both techniques are possible in the case of a differential input. For example, in the op-amp Schmitt trigger, they lead to two versions known as an inverting comparator and a non-inverting comparator with hysteresis. In the case of a single-ended input (fixed threshold), only the second version is possible.

Once helped, the input voltage "moves even further forward " from the threshold by a jump... and when it begins to return, the element switches later. Then it "jumps forward" but in the opposite direction. This behavior is known as "hysteresis"... and it is a kind of memory.

This was my philosophy about circuits with hysteresis as I have presented it, ten years ago, in the Wikipedia page dedicated to Schmitt trigger - https://en.wikipedia.org/wiki/Schmitt_trigger#Fundamental_idea

Now it remains only to see how it is implemented in this mixture of elements...

(By the way, this technique is called by the boring name "positive feedback"... or more precisely, "reinforcing positive feedback" :-)

Now about the specific circuit implementation... I share the Joerg Fricke's explanation and will only enlarge it with a few observations...

Understanding this weird circuit solution is hampered by intertwined connections. However, let's try to trace them by finding familiar circuit solutions...

CENTRAL PART. In the center of the diagram, we see the differential pair of two source-coupled transistors (M1 and M2) with a common dynamic source load (the current sink I1) .

LEFT HALF. M1 drain current is first mirrored by the upper left current mirror M3-M5 and then by the lower current mirror M7-M12. Then it "struggles" with the oppositely changing current set by the output (M10) of the top right current mirror M4-M10. Actually, the current is the same... only the voltage of the common middle point vigorously changes. Thus, M10 and M12 form the so-called amplifier stage with "dynamic load" that has extremely high gain. Its output is amplified by the CMOS inverter M14-M16 (another stage with "dynamic load) and serves as the output OUTa. Really, it's a little embarrassing that the output (M1) of the left half of the main differential pair M1-M2 comes out on the right...

RIGHT HALF. Similarly, M2 drain current is first mirrored by the upper right current mirror M4-M6 and then by the lower current mirror M8-M11. Then it "struggles" with the oppositely changing current set by the output (M9) of the top left current mirror M3-M9. As above, the current is the same... only the voltage of the common middle point vigorously changes. Thus, M9 and M11 form another amplifier stage with "dynamic load" with extremely high gain. Its output is amplified by the CMOS inverter M13-M15 (another "dynamic load") and serves as the output OUTb. It is embarrassing as above that the output (M2) of the right half of the main differential pair M1-M2 comes out on the left...

Now let's see how the general "helping" idea is applied to obtain the so-desired hysteresis...

As Joerg Fricke noted, for each half, a part of current proportional to the output voltage helps the respective drain current proportional to the input voltage. The two currents (main and "helping") are summed by connecting their transistors in parallel (M1a to M1 and M2a to M2).

Of course, a simplified block diagram will help understanding...

Cyril Mechkov Thank you so much Sir for taking out time to analyse circuit and to give a detail answer. It's really helpful for me.

One thing I was confused was about M9-M11 or M10-M12 as common source stage amplifier with dynamic load but i guess what you are calling SO CALLED AMPLIFIER stage is making a "common source Amplifier stage" right?

Second thing, The inverter is added to comparators for gain and to decrease slew rate: can you kindly comment on why you wrote the word "Dynamic load" with inverter stage?

Hi Adeel Ali,

This is a clever and beautiful (fully symmetrical) circuit that is invented by someone with a very good imagination... and it was a pleasure for me to unravel its secret.

M9-M11 and M9-M12 are the same complementary MOSFETs as the classic M13-M15 and M14-M16. The only difference between the two topologies is that the gates of the first pairs are separated while the gates of the second pairs are joined... but they are controlled in the same way.

As you said, each of these pairs can be considered as a common-source amplifier stage with dynamic load. But this dynamic load is not a simple "constant dynamic load" (constant current source) but rather an "oppositely-varying dynamic load" (varying current source).

In fact, in this completely symmetrical structure, the lower and upper transistors simultaneously try to change the total current but in different directions - if one wants to increase it, the other decreases it and vice versa. I intuitively explain the operation of this structure through the concept of "dynamic resistor" (dynamic potentiometer) ... but for some reason (incomprehensible to me) it is difficult to accept by people.

Regarding the CMOS inverter, as I already said above, it is the same amplifier stage with dynamic load since each of the transistors serves as a dynamic load to the other. There are analog applications where the CMOS inverter is used as an amplifier (with an appropriate biasing in the middle of the range).

Maybe a related question about CFA would be interesting for you: https://www.researchgate.net/post/What_is_the_truth_about_the_exotic_current_feedback_amplifier_Is_it_something_new_or_just_well_known_old_Is_it_really_a_current_feedback_device

Cyril Mechkov Thank you Sir.

This was one best discussion for me :)