I simulated a CMOS design in 45 nm technology by varying the temperature. The power and delay is affected by temperature. why it happens? what is the reason behind it.
Your question is basically 2 questions, let me answer them separately.
1. Why does the power go up with temperature ?.
- The power is basically 2 parts:
- The Dynamic part, ie the part of the power that is due to the circuit switching, and
is proportional to the clock the circuit is running on. This is more or less flat, does
not depend on temperature.
- The static part, also called the leakage power. This is due to the current that keeps flowing through the MOS transistors when they are in the off state. For the MOS, the off state more or less proportional to:
exp( kappa * (-VT)/Vt) with
VT : the threshold voltage. Of the order of 0.5 Volt for some transistors (low leakage
transistors), of the order of 0.2 Volt for fast transistors
Vt = kT/q, with k: bolzmanns constant, T absolute temperature, and q the charge of the electron
kappa: The ratio of gate capacitance to total capacitance.(about 0.8).
The leakage increases with temperature, because of the temperature dependency of Vt. As there is an exponential function involved, the effect can be very pronounced.
2. Why does the MOS become slower with temperature ?.
This is because the electron mobility reduces with temperature. As a result, the current carrying capability of the transistors reduces, and this leads to the circuit becoming slower.
The answer of Henri is very satisfactory however i want to add an additional losses in CMOS inverters. It is the shoot through losses during the change of the state of the pull up and pull down transistor. In this transition period the two transistors are on and makes a current path from the power supply VDD rail to the ground.
It can be expressed by Pst= VDD^2/ the sum of rON of the two transistors, the p and n MOS. This power will decrease with temperature as temperature increases because the on resistance of the MOS transistor increases with temperature.