Recently, some papers investigated the steady-state performance of the control charts. They claimed that steady-state performance should be preferred over zero-state performance. In steady-state, some in-control samples (ICS) are generated before a shift has occurred in the process and conditional expected delay is calculated.
Questions
1. Is conditional expected delay=ICS+ARL1? where ARL1 is the average run length of zero state. If ICS=0,conditional expected delay=ARL1???
2. We can say that zero-state is a special case of steady-state??
3. Do Zero state control charts have no benefits?
Your feedback will be highly appreciated