In general, this is NMOS technology hold the majority carrier of electron which have mobility of 1400cm^2/V-s, compare with the PMOS's majority carrier of hole mobility which is 450cm^2/V-s only, there is NMOS carrier mobility is highest than PMOS carrier mobility, meaning that NMOS technology perform well conducting, that is why NMOS is preferred. Right?
Other than that reasons?
The numbers you quote are the bulk mobility numbers. Mobility in a MOSFET is much smaller to begin with. But yes, in the absence of strain, NFETs are roughly 3x stronger than PFETs. But this is not just because of the mobility difference. In older technologies PFET series resistance is also higher than NFET's. In newer technologies (typically 45nm and smaller), strain engineering is widely used, and PFET performance is close to that of NFET.
Thanks you for your replied, Is the bulk mobility refer to the body substrate mobility?
There is the about material properties itself?
Does any reference or related publication for further understanding?
Area for PMOS is almost three times higher than that of NMOS for symmetrical characteristic. This results in higher chip area, series resistance, speed degradation and many other complications.
Digital IC Design by Ken Martin is good reference
What matters in a MOSFET is the carrier mobility in the inversion layer, which is different from the value measured in a bulk semiconductor. Here is a good reference:
http://dx.doi.org/10.1109/16.337449
Savita Maurya, that is why we use 3 contacts active area diffusion with metal on PMOS area to balance with NMOS for this 3 times?
Like this my design below?
Presentation 1 Bit Comparator CMOS 90nm Layout Design
Please note that this is only valid for older nodes. As I noted earlier, in the recent nodes PFET is almost as strong as NFET. So, the layout ratio does not need to be 3x. Something close to 1.3x is more common.
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