Port mapping refers to the concurrent statements and process refers to the sequential statement. If there is a data dependency between the blocks of the concurrent statements, each block itself is a concurrent statement and the entire flow becomes sequential because each block output goes to the input of the next block. In that case why can't we include these concurrent statements inside the process? I am confused and I don't know the reason for this.
PORT MAP statement is used to define connections between design units - components. That's all.
Portmap is just using(calling) the already existing digital circuit in other words declaring input and output pins of a circuit. In process u r just describing the function or behavior of declared circuit. Moreover VHDL/Verilog are not high level languages to define any variable anywhere else in the program.
Process statement is a concurrent statement. Inside the process statement only the sequential statements will be allowed. Port map is a concurrent statement. So it is not possible to declare the port map(concurrent statement) inside the process statement
Dear Anand are u experienced in VHDL. please read VHDL text book by pedroni and try the sample examples in that using both behavioral and structural modelling of the designs. that will give you more insight into the hardware modelling using VHDL
Port mapping is not a statement, it is a technique to connect your hierarchy in the design.
The below link is useful
http://vhdlguru.blogspot.in/2010/03/usage-of-components-and-port-mapping.html
Port map is only used for physical signals and while process is a virtual operations that use variables which requires zero time to execute ( concurrent statements)
Port map is a concurrent statement. it is used to refer existing hardware ports. while, process contains sequential statements which takes very less time to give the results.that's why port map is not compatible under process.
- Badges
- Science topic
- Similar topics
- Social Psychology
- Attitude