P3HT solution was spin-coated on a pre-patterned BCBG type transistor. The thickness of the film was measured at around 30 nm. While heavily doped Si is used as gate, the source and drain contact pads are Ni and the gate dielectric is silicon oxide with thickness of 90 nm. HMDS was spin-coated prior to active layer deposition. The channel length is 40um, and the width is 10mm (interdigitated electrodes). The threshold voltage is in positive scale at around 7 V. What is the reason behind such high threshold voltage?
Dear Ashutosh Panchal,
The threshold in your case is determined by the dielectric layer and low mobility of organic semiconductors. If you want to make low threshold OTFTs, you need to use a much thinner dielectric layer. There are a lot of publications regard such issues.
Hope it helps.
Actually, the dielectric thickness could be not the problem. We abtain Vth of about -10 V with 600 nm of Cytop as gate dielectric. How do you calcolate the Vth?. The lost of saturation of the output characteristics could be due to high contact resistance. Did you try to use a thiol SAM (as PFBT) on the gold electrodes ?
Luigi Mariucci Could you please tell me which region to take the slope from (in the transfer curves) to extract Vth? It seems like we made a mistake. We deposited HMDS prior to the application of P3HT.
- Badges
- Science topic
- Similar topics
- Chemistry
- Nanotechnology
- Nanostructures
- Thin Films