By measurement, we found that the MOS capacitor (n poly, n junctions, n well) has much higher gate tunneling current than does NMOS transistor in negative biased state, why? We think they should have the same gate tunneling current. The oxide thickness is 6.2 nm. The source, drain and bulk of the devices are grounded, and the gate is negative biased during the measurement.
Dear Tillmann Krauss,
Thanks very much for your reply.
1. The band offset does exist, but according to the theoretical deduction, in negatively biased state the oxide potential difference Vox should be approximately |Vg| - Eg/q if the gate is n-type, no matter n-type or p-type of the bulk. Thus the electric field across the oxide (Eox) of MOS capacitor should be the same with that of NMOS transistor.
2. The samples are fresh without any stress before, so we believe the trap effect can be ignored in this measurement.
3. We sweep the Vg from -5V to -10V while the S/D/B are grounded during the measurement , and the Ig of MOS capacitor is about 5 times of Ig of NMOS transistor. This is strange and we cannot explain it now.
4. The channel size of the samples under test is 1um x 1um, and the edge leakage phenomenon is not observed by comparing current vs. area and current vs. edge length @constant bias.
I'm looking forward to your new suggestions.
Sincerely,
Cong Li
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