Conditional Jump instruction normally requires 3 machine cycles(10T), if the condition is true. 1st machine cycle is for opcode fetch another 2machine cycles are for memory read.

If the condition is false it requires 2 machine cycles(7T). One machine cycle is for opcode fetch, another one is for memory read.

Refer the link for more details:

https://books.google.co.in/books?id=Rs6r3Ghjn1wC&pg=RA1-PA44&lpg=RA1-PA44&dq=MACHINE+CYCLE+FOR+CONDITIONAL+JUMP+CONDITION+FALSE&source=bl&ots=Iu6RtOj2_N&sig=eOQ4Uf2FMzRTWUa-k3GC6ZuY0gE&hl=en&sa=X&ved=0ahUKEwiTxO7htaLQAhWJNpQKHQjyDWEQ6AEIKDAC#v=onepage&q=MACHINE%20CYCLE%20FOR%20CONDITIONAL%20JUMP%20CONDITION%20FALSE&f=false

Dear Aparna Moorthy,

No, the decoding and execution parts are not related with the machine cycles in the timing diagram. I have attached the screenshot.

Go through the book Elements of Microprocessors By D.A.Godse A.P.Godse by following link given:

https://books.google.co.in/books?id=8LqTavxvspwC&pg=PA238&lpg=PA238&dq=8085+timing+diagram+for+conditional+jump&source=bl&ots=NUVYIZKUEJ&sig=Gi_y_ZOH74NmJt8aFaHeK7RDRPw&hl=en&sa=X&ved=0ahUKEwjk68CUs6fQAhUBNY8KHas9AQQQ6AEIJzAC#v=onepage&q=8085%20timing%20diagram%20for%20conditional%20jump&f=false

Dear Krishna Kanth,

I hope you have your answer by now from Saranya Madam and Aparna Madam.

I still am trying to explain the reason for conditional branching instruction to follow only 2 machine cycles instead of 3 if condition is not met. Why isn’t  it 3 instead?

The explanation:

First of all we need to keep two things in mind

1. Each instruction has opcode fetch cycle where in first two clock pulses the memory is fetched for the opcode and it is placed on the data bus and in next clock pulses it is loaded into instruction register and subsequently to instruction decoder for interpreting the instruction.

2. The program counter always points to the next memory location from where an 8 bit data will be fetched. Processor always fetch the program counter value either as opcode fetch or normal memory read as per the previous fetching and the program counter value will automatically be incremented by 1.

Now in connection with the answer of the question:

When the opcode for a conditional jump is being fetched the PC value is pointing to the higher byte of jump address. After the 4th CP the processer automatically starts fetching the memory location pointed by the PC (Lower byte ) as a simple memory read and PC is auto incremented by 1 but as soon as the instruction decoder completes the interpretation of the conditional jump and finds the condition to be false then processor finds it unnecessary to fetch the Higher byte of address which is currently pointed by the program counter and the PC value is incremented by 1 again to point next instruction (i.e. an opcode instead of Higher byte). So at false condition there are two machine cycles, i.e. OFC + Mem read (unnecessary but have to wait to finish the cycle)

I will be glad if this info helps.

Thanks