I have implemented a 3-Ph PLL block in simulink as shown in the picture. The output contains a lot of spikes. Can anyone try to explain why I am getting the spikes?
The output of the phase detector is a necessarily fast discrete-time signal i.e. rapid pulses. The derivative part of the PI block (PID controller) is detecting the edges in that output. The (1/s) block is a standalone integrator which you may be hoping (?) to recover the error signal. You could try one or all these following steps to remove the spikes:
1. tune the PI block parameters with reduced derivative gain
2. insert a low-pass filter with a cut-off frequency lower than the repetition rate of the spikes. Place the LP right after the phase comparator (before the PI).
Richard Ocaya Thank you for your suggestion. I tried that but if I use a second order filter for the measured voltage and current signal whole control systems gets uncontrolled. Could you help me which exact block should I use and what should be the cutoff frequency?
Filters matter as they introduce poles in the loop that can lead to control issues and stability i.e. oscillations. Therefore the order and type of filter used matters e.g. is it Bessel, Chebychev, Butterworth, etc? Without knowing all the parameters in your blocks it’s hard to assist you. In any case, have you tried the alternative of lowering the derivative gain? Here is a link to a PDF article that you will find useful https://www.controlglobal.com/assets/digital_edition/2019/July/filtering.pdf