Hi Ronaq Nazir ,

in order to make specific suggestions one needs to see the schematics of your setup as well as oscillograms of the signals.

General idea: Something might go wrong with DESAT; did you look at the /FLT outputs?

Hey Joerg Fricke,

thank you for your response!

I can share the oscillogram with you at this moment.

I have grounded DESAT and there are no /FLT outputs from the driver as well.

Hi Ronaq, its a little hard to guess at without more detailed information, what does the oscilloscope trace show?

I would start by trying to debug your circuit. Run a few quick programs to pulse your gate drivers individually and see that they are functioning correctly. Have you connected all the input pins the same?

Hi Ronaq Nazir ,

I second Phil Denby . As I wrote earlier, a sketch of your setup would be fine but even a purely verbal description would be helpful.

Does the oscillogram show the output signals of the drivers? The state 0000 appears for about 100 ns around -500 ns. What do you expect instead?

I have edited my question and added more details to it.

All my gate drivers are working completely fine @Phil and I am pulsing each gate driver from a separate pin of FPGA. Attaching a block diagram of my circuit.

Hi Ronaq Nazir ,

now the problem (not yet the solution) becomes clear:

The positive edges of outputs 1 and 2 are about 350 ns delayed as compared to the negative ones of output 3 and 4.

Looking at page 8 of the datasheet of the gate driver, the only times of this order of magnitude are related to DESAT and /FLT. You wrote that your DESAT inputs are connected to GND ... they should have no effect.

The next question that comes to mind is: How does the counterpart look like, i.e. negative edges at 1 and 2, positive edges on 3 and 4?

Hello @Joerg,

yes you got it right.

I can share the results for the counterparts as well.

Hello Ronaq,

obviously, all four gate drivers introduce a delay of about 350 ns (additional to the usual delay) for the low-to-high transition. Up till now, I have no idea why.

If I understand correctly, the FPGA is connected to the drivers via single lines (as opposed to differential signals), probably driving the IN+ inputs. I assume that your oscillograms of these signals were taken while the drivers were connected. Did you connect the IN- inputs to GND1?

Secondly, I understand that the output signals /FLT and RDY are just left open. Could you please take an oscillogram of the input signal to and the signals /FLT and RDY from a single gate driver? (If both /FLT and RDY show just a stable "high" before and after the input edges of both polarities there is no need to share the oscillogram, of course.)

The website https://electronics.foxping.com/ (link to YouTube video clips) => 3.5 Electronic FETs (Field Effect Transistors) ... 3.6 Electronic JFETs (Junction Field Effect Transistors) ... 3.7 Electronic BJTs (Bipolar Junction Transistors) ... could provide some insight.

Clyde Eisenbeis : I'm pretty sure this is not a general electronic problem but is somehow caused by "mistreating" the NCD57001.

Ronaq Nazir : Did you already measure /FLT and RDY? If so what did you see?

Another point comes to mind when looking at your pictures: Something is wrong with your voltages. Inputs: The input voltage should be certainly always positive, and the difference between low and high has to be several volts. Outputs: The low level of the output voltage might be negative but the difference between low and high should be more than 13 V. PS: I just discovered that you use AC coupling, at least for the input signals; that explains the negative voltages. But in cases like this, AC coupling has one disadvantage (hiding the DC component), and no advantage whatsoever; therefore I would use DC coupling in the future.

Perhaps you are using 10:1 probes but the scope is set to 1:1, and this explains the low amplitude.

Additionally, which values have VDD1 with reference to GND1, and VDD2 and VEE2 with reference to GND2? (just measured with an ordinary multimeter)

Thanks Joerg Fricke for the valuable suggestions.

The IN- is connected to GND1. The coupling has been changed to DC and attenuation to 10x.

Regarding the FLT signal, it stays at stable high when the pulses are given.

Clyde Eisenbeis: Thanks for sharing but it didn't help.

Hi Ronaq Nazir ,

IMHO, what to do next depends on the ultimate purpose of your circuit:

If it is just meant to be used by you for a short duration in the laboratory: You could accept the delay by the drivers of about 350 ns for positive edges, and change your FPGA design accordingly, i.e. by delaying the negative edges within the FPGA by the same amount of time. If you are working quite independently and the focus of your work is not on the circuit: Better don't mention the problem and your solution in publications. If someone is supervising your work you'll have to admit implementing a not quite satisfactory workaround.

If this circuit is meant to be duplicated and sold to resp. used by others: All the NCD57001s should work like the datasheet says. I'm still certain something is wrong with the conditions around the drivers. What about the RDY outputs? One possibility: The traces between the nearest capacitor and the pins VDD2 and VEE2 are too long or the capacitance is too low. So, during switching the IGBTs on, the supply voltage at the pins drops below 12.5 V, and the undervoltage protection becomes activated.

If I don't miss something, you didn't say yet if the posted output signals are taken with or without the IGBTs connected. If with, how do the outputs look like without IGBTs?

Thanks Joerg! The problem has been solved.

The gate driver has been replaced by Texas’s iso5852s and it executes 4 step commutation perfectly.

Hi Ronaq,

thanks for sharing your solution!

So, on the positive side, your problem is solved; on the negative side, we'll never know why the NCD57001s behaved as they did. :-)

Good luck with your project!