Large values of resistors and capacitors are hard to match in the fabrication phase. It will create some systematic mismatches. So how to avoid those kinds of mismatches in case of current-mode configurations? And what should be the acceptable limit of %THD under this condition?
Thanks in advance!
Dear Shekhar suman Borah
Welocme
May I give some conceptual answer to your question. It is so that there is always fabrication tolerances among the elements of the integrated circuits because of the fabrication tolerances. These tolerances are geometrical and spatial variations in the semicondcutor layers.
So, as you correctly observed as the size of the elements gets larger the variations get more.
So, in the design one has to avoid the use of large elements.
There is also circuit techniques that can be used to increase the matching among current sources which is to refer all intended current sources to the same reference and build current mirrors for this same reference.
One can also add trimming methods to counteract the fabrication tolerances.
You can your self thought how to counter act the fabrication tolerances by making intensive sensitivity analysis.
As for the allowed tolerances, it is a matter of system performance parameters.
The allowed tolerances is a system performance issue.
Best wishes
Dear Shekhar suman Borah
Welocme
May I give some conceptual answer to your question. It is so that there is always fabrication tolerances among the elements of the integrated circuits because of the fabrication tolerances. These tolerances are geometrical and spatial variations in the semicondcutor layers.
So, as you correctly observed as the size of the elements gets larger the variations get more.
So, in the design one has to avoid the use of large elements.
There is also circuit techniques that can be used to increase the matching among current sources which is to refer all intended current sources to the same reference and build current mirrors for this same reference.
One can also add trimming methods to counteract the fabrication tolerances.
You can your self thought how to counter act the fabrication tolerances by making intensive sensitivity analysis.
As for the allowed tolerances, it is a matter of system performance parameters.
The allowed tolerances is a system performance issue.
Best wishes
Are you talking about THD = Total Harmonic Distortions? Usually THD is minimized via deep negative feedback. Some small mismatch/variations in the values resistors/capacitors used for that feedback only affects value of the gain not linearity. THD for even harmonics (mostly second harmonic is of interest) can be affected by asymmetry in differential/balanced schemes however again, it is mostly suppressed by linearization via negative feedback.
Aparna Sathya Murthy Ma'am, thank you so much for your response.
Nikolay Pavlov Sir, thank you so much for your response.
Yes, I was talking about total harmonic distortion. I have observed during my research that as the frequency increases (in various kinds of oscillators), %THD also increases, although the value of R and C can be minimized by scaling. As per your suggestion, by using deep negative feedback I will try to minimize the %THD.
Sir, is this also similar for single-ended configurations if I don't consider the differential designs?
Shekhar suman Borah Yes, single-ended is same. However, I mostly had in mind amplifiers not oscillators . Oscillators have to be non-linear ( that how they stabilize the amplitude). To reduce THD in oscillators one can use mostly two ways: increase Q-factor (if resonant tank is used) or introduce inertial non-linearity.
Since the oscillators are large signal devices, then the major method to suppress the harmonic distortion is to use filters at the output of the oscillators.
The oscillators are positive feedback circuits. Negative feedback is used with amplifier.
But your initial question is out of context of your subject!!
Best wishes
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