POCl3 emitter is formed on both side of Si wafer after P-diffusion process. This step yields n+pn+ structure. I would like to know how I can protect the emitter on the front side of wafer, using a simple technique, against the etching effect of NaOH or KOH solution. The aim is the obtaining of a simple junction n+p.
Dear Nabil,
In order to protect the front side of your wafer against KOH etching, you can deposit a bilayer silicon nitride/silicon oxide. But I would recommend to change the process and not to dope the backside by protecting it with a thermal oxide.
Best regards
David
Hi David, thank you for your answer. Yes the technique that you recommended sounds more interesting, however, I think that the thickness of the thermal oxide must be optimized as a protective layer. Please advise!
Nabil Khelifati ,
As per the response of David Quirion , my first suggestion would have been a good quality SiNx layer.
What is the thickness of the POCl3 layer on the backside? The suitability of different passivation layers will depend on this thickness.
These may help you
KOH ETCHING OF SILICON, by Ying Wang
Available @ http://archives.njit.edu/vol01/etd/2010s/2016/njit-etd2016-062/njit-etd2016-062.pdf
Wet chemical textures for crystalline silicon solar cells, by Jose Nestor
Availiabe @ https://pdfs.semanticscholar.org/f900/fbd144441466856751063450492cdb61a509.pdf
Dear Nabil,
The exact thickness of silicon oxide depends on your process as a whole. It is impossible to advice a value from scratch. In any case, first thing you need is diffusion coefficient of phosphorous in silicon dioxide: you may find interesting information in the following document:
http://www-eng.lbl.gov/~shuman/NEXT/MATERIALS&COMPONENTS/Xe_damage/Diffusionin%20siliconpdf.pdf
Best regards
David
Dear Nabil,
Welcome,
The colleague gave solutions to protect the back side from being doped by phosphorous during n emitter diffusion by masking the back side with sufficient thickness of SiO2 or Silicon nitride. The sufficient thickness is that required to prevent the the concentration of phosphorous diffused through the mask layer to be much less than the background layer of the wafer. Knowing the temperature and the diffusion time one can determined the required mask layer thickness.
Let us return to the protecting of the front emitter layer during etching of the backside, the simplest method is to cover the front layer by an adhesive tape as TESA tape. It is resistive against etching of the Si etching solutions.
Best wishes.
You can also use Apiezon wax. We used it to protect one side of silicon wafers from etching.
Best wishes
Hi David, thanks a lot for the information and the interesting document. sure, I will used it to calculate the adequate thickness!
Dear Prof. Abdelhalim, thank you for your response. the suggested method based on adhesive tape looks also simple and easy. please, could you give us the full name (reference) of this material and the fabricant(s), if possible? thank you in advance!
Hello Nabil Khelifati ,
Although not entirely resistant, Kapton tape (polyimide) should also work for short etch durations. See the attached chemical resistance brochure for more details. Kapton tape is on the 11th column. You will normally find this tape laying around in most laboratories.
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