The popular used mechanism to recover from error in high-end CPU is by adding error correction code(ECC). But, I don't think microcontroller also uses ECC to recover from error because adding ECC feature to MCU based system will incur extra energy overhead which lose the purpose of saving energy. So what is the suitable mechanism to recover from error in MCU based system? Some references will be helpful.
It's watchdog. If a program inside MCU runs correctly, it takes care the watchdog. If the program faces some errors, it can not take care the watchdog. The watchdog will output a reset signal, and then the MCU will restart.
Hi Rujun Chen,
Thank you for your answer. The watchdog module definitely takes care the system failure in MCU. But, what I meant is the memory part (sorry I didn't specify it in the question). The flash memory in some MCUs has something called Memory Integrity Detection (MID) to detect and handle failures in flash memory. What about SRAM memory in MCU?What kind of mechanism used to handle error in SRAM?
Dear Rizal Tanjung,
To my knowledge, there exist no special mechanism used to handle error in SRAM. I think a watchdog is enough for any error inside MCU. If there exist a error in SRAM, the program of a MCU may run out of control. So the program can not take care of the watchdog and the watchdog will reset the MCU.
For smaller microcontrollers, the watchdog timer is the main protection mechanism; and not properly understood by many coders so often not implemented (which can then cause lots of problems later on with erratic processor behaviour from unintended consequences).
Some processors have things like Divide by Zero exception interrupt, which again need to be implemented properly to be useful. Hint; use floating point for ratiometric measurements from instrument sensors, that takes care of the divide by zero thing!
More complex microcontrollers e.g. The ARM 7 series can have a Memory Protection Unit which may include things like abort status and misalignment detection.
High end microcontrollers, e.g. ARM 9 and the multicore processors in phones, will have a full memory management unit which will allow for virtualization and full protection from errant code activity (assuming the programmer takes care to implement this properly).
Note that "back in the day" it was common to do a SRAM walking 1s and 0s and an EPROM program memory checksum tests on power-up. EPROM checksum testing was particularly important as they are often subject to long term degradation. Of course, cramming all this in on top of the regular code in a 2716 ERPOM's 2K bytes of storage could be interesting. Done in assembler of course :)