The achievable DC gain highly depends on the technology you are using, even with the same configuration/topology. For instants, the said folded-cascode opamp can achieve ~100dB DC gain with dated technology nodes (e.g., 0.35um CMOS), however, the same folded-cascode opamp can only achieve ~70dB DC gain with deep submicron CMOS (e.g., 65nm CMOS).
Also, as Thomas has pointed out, the DC gain is also ascertained by the transistor geometry in your opamp. If high DC gain is the primary design consideration for your opamp, a common practice would be adopting transistor with long channel length, because it offers high output resistance; the drawback/tradeoff would be the limited bandwidth.
Dear Norhamizah,
you can find a complete design example in the given link below. The presentation in the link contains complete analysis of the folded cathode circuit. The low frequency gain as hinted by the colleagues depends on transistor biasing in addition to the W/L ratio of the transistors. Higher gain requires high Gm for the amplifying devices and high resistance of the load transistors.
The gain of the amplifier= gm1 x ro, where gm is the transcoductance of transistor 1 and r0 is the output resistance of the amplifier.
http://www.phys.hawaii.edu/~varner/PHYS476_Spr10/Lectures/lecture_7.pdf
best wishes
Noted. Thank you for the answers given. I really appreciate those. :)
As for your information, the technology used for the opamp is 0.18um CMOS technology. The high DC gain is the primary requirement as I am going to implement it in 8bits Pipelined Analog-to-Digital Converter (ADC). If the DC gain is not high enough, then it will affect the performance of the ADC. So now I am trying to have the opamp to have the maximum dc gain and see how the ADC performs. It seems difficult to have dc gain higher than 40dB by implementing the configuration (as attached). But, I am not sure, this problem might be happened due to the way I design it - not very good.
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