In April, TSMC announced that they would begin 10 nm production in 2016, followed by 7 nm production in 2017.
Which do you think is the most restrictive parameter to go down to the following node and why? Power density, power supply voltage, channel length, lithography technology, oxide thickness, propagation delay in interconnects, capacitance of the MOS, mobility of the transistor.
Dear,Christian Pinto Gómez!
Your question not on my specialty.
Yours faithfully, Tsiuri Ramishvili
As we scaling down there are obviously changes in the MOSFET parameter. The next step to this will be the Single Electron Transistors.
Tunneling. For example, scaling down the channel length increases the direct source-to-drain tunneling, whereas oxide thickness scaling increases the gate leakage.
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