It seems you did not provide signal activity file to the tool that is why these results does not mean anything related to your design's power consumption performance. You should first perform a post p&r timing simulation with the option "generate activity file" like .vcd or .saif. Then you should provide this activity file to the power analyzer. If you run the analysis after that then yu will have some interesting results.

• Anıl Çelebi sir i while doing power analysis i upload .vcd and pcf,ncd file but it gives some error i attach my test bench and generated error along with this post. plzz guide me how i will proceed further, error  written in attach file are error generated during power analysis

Hi Ritika Khurana,

Let me first tell you the simple procedure of using the Xilinx XPower Analyzer (for understanding) and then some information on that.

NOTE: To measure the power values at different frequencies, restart the XPower Analyzer to get correct values. If you change the frequency many times at a single run, the power values get added up as the algorithm (according to my knowledge) preserves the previous values of power to add them in calculating the power values of next frequency.

All the best,

Regards

NP.

Regarding the conclusions,

The reported values are for the chip (FPGA) power utilization. The default value of signal activity is considered as 12.5% (Once in eight clock cycles). The quiescent power normally refers to the standby power of the FPGA.

• Clock power is the power consumed by the clock propagation signal(s)
• Logic power refers to the power consumed by the logic blocks (combinational + sequential)
• Signal power refers to the power consumed by the wiring made inside
• IO power refers to the power consumed by the IOs through IOBs
• Leakage power refers to the standby power of the chip (FPGA), which is also called Quiescent power.

I dont think power analyzer is a good tool for power estimation. I am working in this tool and after continuous checking and analysis I am getting some contradicting result. basically power analyzer shows the static and dynamic power with different frequency in different airflow. As we know that theoretically Dynamic power increases with increase in frequency. But in Xilinx power analyzer  Dynamic power decreases with increase in frequency. There are some other problem also in this power tool. so better use Synopsis for power analyzing.

@Prasad N. sir firstly thanx a lot for your  reply which proves really very helpful.

sir i did same thing but i am getting certain error in summary report......and in details i am nt getting any clock option.my  code  is totally combinatonal,it contains adders and shifters only may be this reason.sir i add my test bench and error during power analyzer along this comment.kindly consider it and guide me how i should proceed further.

@Amit sir, ok i will try it on synopsis tool.

Hi Ritika Khurana,

From the error report, I suggest you to change the toggle rate of the signals between 0 and 100%. For more information, you may check the following link.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/isehelp_start.htm#xpa_c_overview.htm

Best Regards.

NP

Hi Ritika Khurana,

For Accurate power analysis, Either  you have to use Cadence tool or Synopsis tool. Because Xilinx power analyzer wont give the accurate power of your design.

@N.Prasad Sir i follow the steps told by you.But please tell me how to generate .saif file. I cant able to generate same.

Kindly check the file page numbers 22-23.

Dear Ritika,

     i am also facing the same problem, what you are facing. i am unable to get it.

Respected professors,

I have a doubt while calculating the power analysis in xilinx vivado 2019.1,the precision is coming in watts.Could you able to tell me how to convert it into mW.likewise whether Altera quartus II is the best tool for the power estimation