I am combining both LNA and band-gap reference module. I need suggestion regarding the following.
1> As there are multiple VDD and GND points, is it a good idea to run parallel slabs of each VDD and GND planes like how its done in digital design?
2> If we run multiple parallel slabs for each power rails and if we keep individual blocks in between in each of those then some of the MOS device currents become opposite to each other. What are the effects that might occur if we don’t maintain same current directions for all MOS?
3> It’s always recommended to have a good coupling between VDD and GND. So if I have M1-8 options then which possible combination of metal options I must consider (ex: M1 for GND, M2 for VDD or M7 for GND, M8 for VDD or M1 for GND, M8 for VDD) ?
4> Regarding 3 by considering maintaining good coupling b/w VDD and GND, I might choose one metal order above or below to one another. If I chose M2 for VDD and M1 for GND then I am unnecessarily providing VDD & GND a highly resistive path but interconnections to modules become easier. Instead if I chose M7 for GND and M8 for VDD, interconnections to lower modules becomes complex but I will be providing lower resistive path for VDD and GND. So which metal I have to choose for these rails and what many factors must be considered?
Thanks and regards,
Vinay Rao.
According to my experience, in RF circuits specially in LNA circuits, you should use ground planes on the top side alongside your circuit and the ground plane at the bottom. It is recommended that you have Co-Planar waveguide (CPW) or Co-Planar Waveguide with Ground (CPWG) where the quasi-TEM waves with terminate properly. If you do it for DC lines, it shouldn't be a problem; in fact it will also take care of the RF leakage that goes to DC supply. Complete ground plane in the bottom should be enough.
Let me know if I have answered you.
@Abhay: Thanks for your reply.
Top and bottom ground planes on either side of the circuit, may be you are referring to provide a shield for LNA against substrate noise coupling. It is true for both board-level designs and on-chip interconnections. But my query is particularly regarding on-chip implementations where options are very much limited.
My query is: In on-chip which metal options need to be used for VDD & GND by maintaining a good coupling (whether we need to trade-off b/w resistivity, interconnections complexity etc.), how to run multiple VDD and GND lines, how current directions affect the performance and what other factors one need to consider (if there are any).
OK. I was considering that ground planes could be used for F as well as Dc. But as you say, there may be some limitations where you have to use signal and gnd line, then even I can follow the question and look for correct answer. :)
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