The low power is important in electronics industry especially in Very Large Scale Integration (VLSI) field. The multiplier utilize multiplication process with 70nm Complementary Metal Oxide Semiconductor (CMOS) technology with a clock period of 2 GHz.
Papers:
A. Karimi, A. Rezai, M.M. Hajhashemkhani.2018. A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power, Integration, the VLSI Journal, 60: 160-166.
O.S. Fadl, M.F. Abu-Elyazeed, M.B. Abdelhalim, H.H. Amer, A.H. Madian. 2016. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model, Journal of advanced research, 7 : 89-94.
Not sure what you are asking. Why do you mention 70nm? The closest node to 70 is 65nm, and even that node is already 10 years old and has no new challenges associated with. What is the relationship of these papers to the mentioned multiplication problem?
There are no challenges. An 8-bit finite field multiplier is about 200 gates. I think 65 nm has a gate density of about 400 kgates/mm2. That is 2000 8x8 multiplier per square mm. What are you after ?. What do you want to do with these multipliers ?. AES ?, BCH ECC ?. Reed-Solomon ECC ?
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