1) Most TTL/CMOS signals are not terminated, and the lines are put without careful concern over the characteristic impedance ( it anyway usually stays order of 100..200 ohm) .

So some ringing is accepted, and it usually rather low as typical transition time of the signal is ~4nS (the fastest are usually ~ 0.5nsec).

4nS would roughly correspond to two-way delay of PCB track of ~30cm length.

The critical tracks are usually kept much shorter, still if one wants to suppress the ringing (e.g. considering EMI issues) what is often recommend is 10..47 ohm SERIES resistor close to the receiving chip ( that however causes some loss in the slew rate).

The matching using parallel load resistor is usually not used as it

a) increases power consumption

b) not that efficient as inputs tend to have ~4pF capacitance already causing noticeable mismatch.

The time critical signals are usually delivered not as TTL/CMOS but as LVDS, PECL or other low-swing, preferably differential signals. Then, usually 100 ohm diff impedance lines and terminations are provided. Some ICs may provide on-chip termination. 50 ohms lines are used for the single ended signals.

2) You have to look at your two-way signal delay (considering reflection), the source and receiver risetime. Note that in deeply mismatched, open-end line exposed to fast signal will produce initial overshoot which for a hort time doubles the signal amplitude. The important factor however is also capacitance of the input.

3) There are plenty of online-tools for that.

E.g.

https://www.multi-circuit-boards.eu/en/pcb-design-aid/impedance-calculation.html

In practice, to make proper matched 100 ohm (differential) or 50 ohm single-ended lines one has to use 4-layers or more layers board assigning one or more of the layers to ground plane.

I would say that these are parasitic high-frequencies and after you test the PCB, you may be able to decide (by test points) where to add a small capacitor (range is low pFs) to create a very high pass filter (but this would be an ad-hoc one - this is from my experience about 28yrs ago). Nowadays after so many simulation packages and software, this maybe done automatically but at that time - I used to do it ad-hoc during "making alive" the PCB. Not sure if this makes sense, I hope that it does.

Adding to the colleagues above, this question is very important and treated in rf circuit design and high speed logic circuits. The treatment is normally based on the transmission line theory. It is so that any metallic path has its own inductance, resistance and parasitic capacitance to the neighboring paths. In the lay out one tries to minimize the length of the path and reduces its parasitic capacitance to the surrounding wires. Ideally these paths are ideal conductors but practically every wire path has an LCR circuit. The parasitic

elements can be considered negligible if they will not affect the signal transmission on them. But if they affect the signal transmitted on them they have to be taken into consideration. Not only this, as the frequency increases and the electromagnetic propagation wavelength decreases such that the length of the path becomes comparable to an appreciable fraction of the wavelength say L< lanbda/10, one has to consider the distributed nature of the path and determine for it a characteristic impedance Z0 and a propagation constant P. In this case it may be suitable to go to micro strip line circuits where one makes a ground plane and a microstrip plane. In this case one can design the circuit according to the microstrip circuit design rules.

I think the rule of thumb is that the length of the path must be smaller than lambda/10 to neglect its effect or it can be considered in a lumped form. One do not need to specify a characteristic impedance except at the terminations where one uses connectors and cables with 50 ohm impedance.

Best wishes

Keep in mind that point-to-point wires between a driving circuit and a receiving buffer with no resistor between does not necessarily constitute a lack of termination. A simplistic schematic review approach may determine there is no termination. However, your receive buffer has termination properties so your transmission line will be terminated by the RC equivalent of the receiving buffer's load characteristics.

Adding this as food for thought. Also, buffers can have built-in termination (on either or both sides) that are not apparent in the schematics. Built-in pullup/pulldown or up+down termination inside the package. Sometimes always there - sometimes programmable. Datasheets, application notes, and handbooks document this.

Speaking of application notes and datasheets - these can be resources for termination values as some reference design may include them. Not something to depend on - but something to look for as a shortcut.

If you have oscillating circuit paths with fast edges (know your design and buffer properties) then these "critical" paths you can punt and add zero-ohm place-holders for termination. It's not practical to add these everywhere - but you can generally cover the "hot spots" up-front. Measure/test for ringing and adjust your termination value to slow down the edges (series) or to dampen reflections (parallel). Your application notes / reference designs will generally give you the answer of the proper termination topology IF your circuit resembles the "expected usage" of a given component. If you are doing something novel - there may not be an application note for this - but high speed digital design rarely has something that breaks the mold of what an application note/reference design would cover.

Measurement of high speed and low voltage circuits has to be done with care. Your probe cannot be too big of a load on your circuit to invalidate the results. The lower the voltage and higher the frequency - the more investment you would need in tools OR switch to functional testing where you are looking at results (effects) rather than the cause directly.

Series terms at the source can slow down edges to help attenuate slew rates. With anything, there's a limit. Series terms can also reduce the energy of the switching event which will benefit by reducing the likelihood of a signal becoming an aggressor to a neighbor (cross-talk). Most "high speed" clocks will have series terms initially loaded with a very low value (or even 0ohm) to allow tuning to compensate for ringing or more rarely crosstalk (as the duct-tape "fix" approach before a next spin where aggressors are rerouted or neighbors are moved away or other mitigation techniques).

Very nice discussions. Thank you all!

Howard Johnson book and/or seminar is an invaluable resource which does help quantify some actionable rule of thumb type approach (and more).

Prof. Zekry already gave the basic criterion as to where a line termination is considered mandatory: trace length < lambda/10 resp. a roundtrip (2 way) time < Tau/5 (Tau: shortest time the signal stays high or low after the transistion).

Considering fast gates with comparably slow signals (might be the case if the focus is on signal delay, not necessarily on signalling ratio), there had been similar rules of thumb to prevent excessive ringing, but at the moment I just cannot remember the critical values for the multiples of the rise/fall times.

Some decades ago, there were "wars of belief" about the best way to terminate the lines:

• starting with the single resistor with a value equal to the characteristic impedance of the line
• via asymmetrical terminations (2 resistors with different values between supply and ground, the midpoint connected to the transmission line) to better adapt for receivers with non-linear impedance
• 'til to a termination where the line and the termination resistor(s) were separated by means of a small capacitor to reduce DC power dissipation.

Could be there were even more terminations schemes, the above are those I remember best.

This was so insightful, I hope I can catch up with all of the new stuff, as I work now in another field, but I agree, band-aid approach is never the best one. If you can find how to optimize it for consistency, that would be the best approach.

Lots of interesting answers here, all with varying levels of correctness. I'll try and clear this up:

1) It depends on the permissible impedance mismatch used in your signalling standard. In reality, the input impedance of your transmission line depends on its length. If the line is very short, then the transmission line behaves as if it has the same impedance as the load once the system reaches the steady state, so the transmission line impedance wouldn't matter. What qualifies as the "critical length" depends entirely on the permissible mismatch between the input impedance, your source impedance, and load impedance. If your permissible mismatch is 2%, then your critical length will be shorter than if the permissible mismatch is, say, 5%.

2) This really expands on the previous question. People quote transmission line critical lengths anywhere from lambda/10 to lambda/20; in reality, there is no specific critical length and ALL pcb traces behave like transmission lines. See this article I wrote for Altium for more information:

https://resources.altium.com/high-speed-design/why-is-there-a-transmission-line-critical-length

3) Proper termination means that the output impedance of the driver, impedance of the transmission line, and impedance of the load are all equal. Some exceptions exist, such as with current-controlled drivers. Always check the signalling standard you are using, or check your component data sheets. Generally, your component datasheets will specify a specific characteristic impedance or differential impedance that should be used along with any required termination to ensure that the load sees the correct type of signal to causing the load to latch and/or switch states.

Hopefully this helps! If you have any questions, drop me an email at [email protected]

Source termination is particularly convenient for high speed CMOS digital lines. The source resistance is made equal to the line impedance, while the receiver is high impedance with a small capacitance. The wave reaching the receiver is reflected and absorbed by the source termination. The driver is loaded by 2*Z0 while the wave is traveling in the line and the load resistance is very high once the wave has returned to the source.

A 74ACnnn buffer has ~20 ohm output resistance and 1nS rise time. It is useful to use ~75 ohm impedance line to ease the load on the driver. In that case, a 55 ohm resistor is placed in series with the driver. The source resistance forms a voltage divider with the line impedance, and a wave of amplitude Vs/2 travels down the line. When it reaches the high impedance receiver input, a wave of +Vs/2 is reflected back towards the source, with the result that the signal voltage at the receiver input appears as Vs. When the wave has returned to the source, it is absorbed by the source impedance and the line then sits quiescent.