Dear All,
Why there is a tappering of the channel at higher bias voltage of Vds in MOSFET?
if we increase vds then it attracts more and more carriers from the channel as compare to source so channel gets tapper
Basic considerations see eg .:
https://www.researchgate.net/publication/281480600_Theory_of_electronic_circuits
https://www.researchgate.net/publication/281492423_Errata_-_Theory_of_electronic_circuits
Book Theory of electronic circuits
Data Errata - Theory of electronic circuits
Dear Manoj,
I would like to add some comments to the colleagues. In order to answer your question, one has to explain the operating principles of the MOSFET. It is so that the oxide capacitance is is biased along the channel from the source to drain by the potential difference between the the gate voltage VGG and the the potential Vx due to the drain to source voltage VDS,
Therefore Vox as a function of x= VGG- Vx - Vth.
Vth is the threshold voltage to invert the channel. And consequently,
QGx= Cox( VGG -Vx- Vth).
Since Vx increases from zero at the source to VDS at the drain, the channel charge QGx will be highest at the source and lowest at the drain side. When we visualize the charge Q of the channel we find that its depth gets smaller as we approach the drain which means that the channel is tapered in the direction from the source to drain.
here i simplified the the analysis and assumed enhancement NMOS transistor.
This effect is explained in the book at the link https://www.researchgate.net/publication/236003006_Electronic_Devices
wish you success
Book Electronic Devices
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