I am designing a 3-stage inverter TIA. The first stage in my design is capable of voltage gain 5x at the maximum(14 dB). I wanted to increase this gain, so I cascaded it with two similar stages. For a first stage alone, the phase margin of the system from stb analysis in cadence is about 96 degree. The three stage cascade on the otherhand has a phase margin of -130 degree indicating unstable system. To tackle this issue, while having the cascade; what is the best way to approach towards bettering my phase margin?

It seems like by varying the feedback capacitor and resistor alone, the phase margin is not improving. So how to get over the low phase margin; any parameters that I need to check/adjust? The figures for the phase and gain (For Phase margin calculation) single stage and 3 stage TIA are attached here.

-Rakesh.