Hi,
I am studying about how we can reduce the extra/redundant FFs from our logic using DC compiler. To understand the same, I instantiated the same design block 2 times in my top, giving it exactly same set of inputs. Output of one of the design was selected based on the select signal. I expected that DC compiler would optimize the design and it would be close to single instance area. The observation were-
1. When design had only combinational logic, It was optimized
2. When design contained sequential elements too, it was never optimized
I checked and verified that compile_enable_register_merging is "True" and so the design should have been optimized even if it had FFs.
I also tested the same with a very simple design. Now the 1-bit input of design was connected to a Flip-Flop (FF1). Output of FF1 goes to two FFs (FF2 and FF3). FF2 and FF3 both are connected to separate output port of the design.
Now, since FF2 and FF3 are exactly the same, I expected the design to eliminate one of these FFs, and the output of this one FF should go to both the output port, but the design was not optimized.
As per the DC user guide, I checked compile_enable_register_merging variable and it was set to True, so the equal or opposite registers (used in the Synopsys document) should have been removed. So, is it beyond the capabilities of compiler, or am I missing to set any setting variable for the compiler.
Please let me know if someone has any inputs on this.
Dear Chirag,
I suggest you to see links and attached files on topic.
http://cseweb.ucsd.edu/~hepeng/cse143-w08/labs/VHDLReference/SynopsysCommandsReference.pdf
https://link.springer.com/book/10.1007%2Fb117024
http://www.ee.ncu.edu.tw/~jfli/vlsidi/lecture/Design-Compiler.pdf
https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-software/max_plus-ii/dcfcall.html
Best regards
Thanks a lot Mohamed-Mourad Lafifi for your answer.
As per one of the attached references (DesignCompilerOptim.Ref.Manu..pdf in the previous answer) pg-144, describes about Merging Equal and Opposite Registers. In my Verilog module, I tried to implement the same, but observed the flops are not getting merged. I also checked my compile_enable_register_merging, and it is enabled (True).
I have also attached the schematic (reg_merge.pdf) post compilation. It would be very beneficial if someone could provide me hints about why this obvious optimization or merging of FFs not happening and how to make them happen?
If you make the select bit constant, the tool can optimize away the other branch that will never be picked. If the select bit is an input, the tool HAS to assume it can later change and therefore cannot remove the logic that appears redundant (but really isn't)
Hi Samuel,
Thanks for the suggestion. But actually, I was exploring the dc compiler optimization capabilities. Also, even if the select bit changes, it should still optimize as the 2 designs were same and were given the same inputs.
Hi All,
I actually found the problem with my design and why it was not optimizing.
I was grouping all paths from clock_pins of all register to data_pins of the registers. This grouping was somehow hindering the optimization process for the registers. After removing this command, the optimization works as excepted.
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