Etching to Access the Quantum Well

Typically, the quantum well should remain intact, and you should not etch down to the well itself.

You need to etch through the top doped layers to define the Hall bar structure but stop at the upper undoped layer or barrier layer. This ensures that the QW remains undisturbed while still allowing electrical access.

If your top layers are too thick, you may need to thin them down selectively for optimal contacts, but excessive etching can damage the QW.

Ohmic Contact Metallization

The metallization should form low-resistance ohmic contacts to the QW electrons. This generally means:Alloyed contacts (e.g., AuGeNi followed by annealing) that diffuse slightly into the structure to reach the 2DEG. Deposition directly onto the doped InGaAs cap layer is usually sufficient, as it allows for carrier tunneling into the QW. Some studies employ deep contacts where the metallization extends into etched regions (e.g., recess etching down to or near the top barrier). Sidewall coverage is generally not necessary unless lateral conduction issues arise.

Hall Bar Geometry and Fabrication Steps

The Hall bar should be designed with well-defined contacts for longitudinal and transverse resistance measurements.

Standard fabrication steps include:Optical or e-beam lithography to define the Hall bar pattern. Wet or dry etching to remove unwanted material (typically using selective etchants for InGaAs and AlAs). Ohmic contact deposition (AuGeNi, Ti/Pt/Au, or similar) and annealing to achieve good electrical connectivity. Dielectric passivation (e.g., SiO₂ or Si₃N₄) if needed for device stability. Metal interconnects and bonding pads for measurements.

References and Guides

S. Datta, Electronic Transport in Mesoscopic Systems (1995) S.M. Sze, Semiconductor Devices: Physics and Technology (2012). "Physics of Low-Dimensional Semiconductor Structures" by J.H. Davies

Dear Yana Suchikova ,

Thanks for your answer.

My Undoped InGaAs layer before the first barrier is 20nm, I will consider etching to 5-10nm to ensure proximity to the QW while keeping the barrier safe.

I usually use Ti/Pd/Au directly on InGaAs for contacts, I will try the same for the Hall bar fabrication

Kind regards