Hello,
Usually, by biasing Vgs < Vthreshold of MOSFET, we can push MOS into sub-threshold region. My curious question is: How much value of Vgs is "good" as a "rule of thumb"?
I have referenced to "Trade-offs and optimization in Analog CMOS design" book, and they supplied a good reference (please check the figure below). It seems to be good from this book is that we should bias MOS such that -4.5nUT < Vgs - Vth < -2nUT, which is equivalent to approximate value in a range of: -163 mV < Vgs - Vth < -72 mV (n is the slope factor defined by EKV model from EPFL, UT = kT/q is the thermal voltage).
Could you guys confirm or give out any recommendations?
Thanks!
Hello,
Since, you are targeting sub-threshold region, I would recommend to run a simulation for your transistor (PDK) and check your current density especially for short channel technology.
I will explain how to use current density methodology as follows:
1)Current density Jd=Id/W.
2) sweep gain Vs. Jd for different L.
3) Select L that give you the target gain.
4) sweep gm Vs. Jd for L from previous step.
5) Calculate the unity gain frequency, Fu=2*pi*gm*CL.
6) Plot Jd Vs Vgs.
7) Select the Vgs that gives you the Jd from step 1.
Regards.
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