Dear Abdelaziz Lberni ,

You have to define at first the parasitic and then you can locate their sources.

The parasitic are normally defined by the associated capacitances to the integrated circuit elements such as the transistors, the interconnects and the resistors. There is also parasitic inductors but they must only considered at very high frequencies. There is also the resistances of the interconnects where they are considered parasitic.

By inspecting the parasitic capacitances one can see that they increases by area of the transistors and also by the peripheral length. As for the interconnect paths,

it is the length and the width of the path that increase the parasitic capacitance.

So, in order to minimize the parasitic you have to:

reduce the layout area.

reduce the layout peripheral.

Shorten the length of the interconnect and reduce its width while keep its resistance below certain acceptable limit.

There are other factors that affect the parasitic but those mentioned above can be considered the major sources.

Best wishes.

Dear Abdelhalim abdelnaby Zekry

Thank you for your answer.

Indeed, I am trying to introduce the layout parasitics in the optimization process of analog circuits. Is there a method to model interconnect path parasitics in the netlist file (.sp)?

Is it possible to model the parasitics extracted from the layout by DRC (Caliber & Cadence)?

Regards.

Dear Aparna Sathya Murthy

Yes, I have Virtuoso and after checking DRC / LVS, I extracted parasitics from the layout.

Now my question is how to model these parasitics in a netlist file (for Hspice) or in schematic (Cadence)?

Aparna Sathya Murthy Thank you for this Tutorial.

Is it possible to model the parasitic capacitances and resistances in the netlist file (.sp) for Hspice?

OK thank you.

I will try