We started importing EDIF from Tanner2016 to OA, to be able to design and to interchange the OA database between Tanner2019 and Cadence IC6.1.8. However the interoperability of this schematics in OA fails!
Any design schematics from CDS are fully readable and fully useable in Tanner2018 and Tanner2019. The same applies also for Layouts and Symbols from CDS into Tanner.
We see OA-interoperability problems when comming with OA-database from Tanner2018/Tanner2019 into CDS 6.1.8. Virtuoso schematic editor:
1.) invisible "ghost" wires: they physically are existing/moveable/contactable, but are not visible
2.) TannerFakeNet wires: where EDIF-Tanner used zero-length net-names directly placed on a block symbol (we corrected it in Tanner and imported anew) after Tanner2019 OA import (which was in Tanner readble) we used the OA database in CDS, but IC6.1.8. did not recognize this short stump/stub and place "TannerFakeNet" in net-wire name light-blue-color (CDS wire default color).
3.) wires carrying "Not Checked Yet" property: which leads to a behaviour, that the whole wire looses its original name (TannerOA) and when this net is connected to a pin, then it causes in CDS an error, because no-net-name wire being connected to a pin. This behaviour does not vanish in CDS when we delete all the wires and redraw the wiring anew.
3A) then we started to delete the pins to be able to overwrite the netname. This did not help, deleting pin leads to still stacking net-name "Not Checked Yet", we are not able to correct the net-name even without pin.
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The most critical problem is the 3.) and 3A)
We further evaluated the behaviour of the lost net-name (Not Checked Yet).
1.) We see, that the untouched schematic in read-only mode, just after being copied directly from Tanner (Win to Linx directory copy) is initially clean. All wires are available, each wire carries its original name.
The problem starts as soon as we open the schematic in CDS in edit mode and run initial check-and-save. This immediately generates the unvisible wires and some wires looses its name (they get the "Not Checked Yet" property). Probably the intial netlisting causes that from the OA database this missing net-name is loaded to the schematic view ???
2.) We deleted sequentially all the pins in CDS schematic editor and running CDS check-and-save, to delete potential source of problems (no pin => not net-name error, and to be able later include new pins per name). When the last Pin in CDS is deleted, then first the CDS Schematic windows crashes and after 10-15 sec also the whole Cadence IC6.1.8 crashes.
3.) we ran "oascan" over the database and it was clean. Also selectively over the destroyed schematic cell. no error, no repair occurs.
4.) we see in CDS Schematic Editor that in the corruct OA-schematic from Tanner2019, each pin comming from Tanner carries 3 additional properties: .
TannerOriginalName = VEEA, TannerPortGlobal=0, Tanner PortType=6.
These 3 properties can be deleted in CDS, but the pin or the whole OA schematic is still somehow corrupted. The OA-resaving in CDS is not able to delete the problem in OA, since even pins without Tanner properties causes schematic errors. CDS never can clean the OA-format problems which occurs when saving in Tanner.
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We see, that any OA database generated in CDS IC6.1.8 is readable, usable in Tanner2019. There are no problems with Layout, nor with Schematic, nor with Symbol. Thus the way CDS => Tanner is working, but the reverse was Tanner => CDS does not work for OA. Thus the OA-interoperability is not working between Tanner and CDS
___________________________________________________________________ We conclude, that there must be a problem in writing OA format or reading the OA with additional feature. But we can not conclude where the problem is located, as we are not familiar with OA standard.
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Thank you very much for any comments in advance.
Further Diagnostics:
We evaluated what happens, when a corrupt OA database (schematic) is used back in Tanner2019.
It means, moving twice the database between CDS and Tanner:
1) original CDS => 2) moved to Tanner2019, saved (? OA format problem?, but is not visible yet) => 3) back to CDS (in read-mode OK, but in edit mode after check-and-save unvisible wires and wires without net-name) OA corruption visible, after check-and-save OA saved anew => 4) back to Tanner2019.
From the two errors we saw in CDS, the first error is also visible in Tanner.
1.) unvisible but existing wires (problem in CDS and in Tanner2019)!!
2.) wires without names (Not Checked Yet) => only in CDS
the 2nd problem is not existing in Tanner2019. Means, in Tanner2019 S-edit
the wires carry their names and Check-and-Save (thus internal netlisting)
can be run in Tanner2019 and does not bring any errors!
The unvisible wires (error 1.) arises in CDS and Tanner exactly on the same
location (5 error location in this Schematic).
Enclosed Figure show the unvisible wire between HW directly on the transistor
and the common HW-rail-wiring below. Unvisible wires, but the connectivity
is given, because blue net-highligthing works! See also the red VEEA net,
it carry the name and here CDS had problem because VEEA goes to pin
and without net-name this wire was not correct @ VEEA-pin. The net-name
loosing is not existing in Tanner2019 after the OA gets corrupted.
The 2nd picture reveals however a different problem: unvisible wire for
2 nets: red and blue. The both NMOS transistors (nhsj1_7_4 and ne5_2)
both miss their source wiring! Net-highligthing shows the source is not
connected (no color) and thus also the Bulk shorted with Source is not
connected (unvisible wire) and thus not highligthed!! somehow this
connection is realy lost and not just "unvisible".
The 3rd figures from CDS show exactly the same location as the 2nd figure.
Here we see the difference in behaviour between CDS and Tanner2019:
the bottom NMOS transistor "ne5_2" in CDS has despite of unvisible
wire their S and B connected and thus high-lighted (white VEE)!
High-lighting was only possible because VEE is directly on a pin and
it is not the 1st pin at which already the check-and-save errors occured.
this behaviour was different in Tanner2019.
The top NMOS transistor "nhsj1_7_4" does not allow any high-lighting,
because in the corrupt OA database any of his wires do not carry net-name (wire without pin => Not Checked Yet).
Dear, Richard Izak !
As I understand your problem, you can't to convert Tanner => OA of cadence properly. But it' s easy to convert Tanner=> cds of cadence.
I have no experience with Tanner, but I have good practice with cadence. As I know Cadence of version 6 does not support CDS format, only OA. While cadence of version 5 works only with CDS format. There is a good conversion toolbox to convert CDS to OA in 6th version of this CAD.
I think you should try to convert Tanner => CDS and try to open this files with cadense 5. And if it is OK, you can use convertional toolbox of 6th version to convert CDS => OA.
Best regards,
Anton
Dear All!
meanwhile we debugged the problem more in-deep and here are the findings:
1.) invisible "ghost" wires are caused by Tanner S-edit 2018.3, since the tool sets for some reason the wire width to zero! Here we wrote a Tcl procedure which can set the wire width > 0 and thus correct this error for each cell view:
proc wiresize {lib cell size} {
cell open -cell $cell
find wire -library $lib -cell $cell -scope all
set wirefound [find wire -count]
puts "$cell: wires found: $wirefound"
if {$wirefound != 0} {
property set Width -value $size -ptype string -display Hidden -whennotevaluated Hidden -units inch -host selection -system
}
set wirefound 0
}
set size 1
set wirefound 0
set lib [workspace getactive -library]
#set cellList [database cells -library $lib]
set cell [workspace getactive -cell]
set cellList {}
lappend cellList $cell
foreach cell $cellList {
wiresize $lib $cell $size
# window close -cell $cell -library $lib
}
3.) wires carrying "Not Checked Yet" property
is a more serious problem. It seems to be incoporated in the OA format which Tanner uses. OA introduce by Cadence seems to be other organized as the OA format recently (2018) introduced by Tanner for schematics. Tanner OA is more like a netlist in OA format....it seems to be evolved from earlier Tanner-used EDIF-format. Thus the connectivity and probably the wire properties are derived from this netlisting.
Whereas in CDS OA there is a storage space for each piece of the wire, for each wire section, carrying informations like: thick/thin wire, bus-extension yes/no, name, color, ....
Adding a wire name to a non-named (net05) wire in CDS can be observed, that within 2 sec the new-added wire names propagates to the next transistor pin and this transistor annotated net-name changes from net05 to new-name. This happens even without running a check-and-save on this schematic, just on-the-fly as the wire name has been added.
Tanner behave here different....
There seems to be a problem of interoperability between the netlist-driven OA database in Tanner, where the property is derived and entailed from this netlist, thus all wiring section carrying the same property, and the CDS OA format as it has been introduced to EDA-semiconductor community, where each wire section has its own property and is saved separately. This is just my opinion, since I am not an OA expert, just an circuit designer using OA-based EDA tools.
Service Requests are filled to Tanner as well as toCDS, lets see whether the problem can be solved....good luck for anyone having similar problems!
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