I know VHDL and did some projects, I am familiar with the hardware design concepts. What i need is a reference book in which i can get the rules in Verilog
something like
It is not possible to assign a wire data type inside always.
All ports are defined as reg data types.
I found this book useful:
Fundamentals of Digital Logic with Verilog Design
by: Stephen Brown and Zvonko Vranesic
As you know VHDL already, I would recommend you to try SystemVerilog.
You can check the "SystemVerilog for design" book by Stuart Sutherland.
http://ieeexplore.ieee.org/search/searchresult.jsp?newsearch=true&queryText=Verilog+HDL
http://www.verilog.net/
http://www.asic-world.com/verilog/veritut.html
these books hopefully can help you:
- System Verilog for Design Second Edition, ISBN: 0387333991
- Fundamentals of Digital Logic with Verilog Design (3rd edition), ISBN: 0073380547
- The Verilog Hardware Description Language (5 Edition), ISBN: 1402070896
The Design Warriors Guide to FPGA's
Device,tools and flows
please have a look at this book.
Hi, I suggest this books:
1-Fundamentals of Digital Logic with Verilog Design --by Stephen Brown, Zvonko Vranesic
2-Advanced Digital Design with the Verilog HDL (2nd Edition) -- by Micheal D. Ciletti
3-Sequential Logic: Analysis and Synthesis -- by Joseph Cavanagh
4-Computer Arithmetic and Verilog HDL Fundamentals -- by Joseph Cavanagh
Good Luck
Check these:
Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar - excellent book
FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version by Pong Chu - many useful examples
Check this out:
Advanced FPGA Design: Architecture, Implementation, and Optimization
By Steve Kilts
Plenty of good books out there, mentioned by others.
I suggest you have a look at what sunburst offers: http://www.sunburst-design.com/papers/
Over the years they wrote several papers about the language, what is good and what is bad about it. could be an interesting read if you have the vhdl background. Plus, there is the IEEE standard, useful for when you have punctual questions.
My suggestion is to read some tutorials and/or books on Verilog and then ask specific question. This is RESEARCHgate.
The Verilog always procedural block is a equivalent of VHDL process. With always you can use only procedural assignments i.e. assignments to regs (reg is similiar to VHDL signal).
The assign statement is a so called continues assignment. Can be used to assign wires only.
Some very good books that you could find interesting for learning Verilog could be:
1. Advanced Digital Design with the Verilog(TM) HDL, by Michael D. Ciletti.
2. Verilog HDL: A guide to digital design and synthesis, by Samir Palnitkar.
3. A Verilog HDL Primer, by J. Bhasker.
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