A monostable circuit can be typically implemented using an EXOR Gate with delayed pulse train as inputs. This way we can generate very sharp pulses at the Leading edge and trailing edge of the leading input pulse. The output can be ANDed with either of the input Square wave to generate only the Leading edge /Trailing Edge pulse as required........
But am envisaging the implementation of ONLY Leading edge pulse without any extra circuitry such as AND gate.
Can anybody suggest!!
Thanks in Advance.
Muralidhar.M
I'm not sure if I understand the problem correctly because my solution seems a bit too simple: Just feed the not delayed and the inverted delayed pulse train into an AND gate instead of the EXOR gate.
Or, if for some reason you want to get rid of AND gates in general: Apply De Morgan's laws, and feed the inverted not delayed and the delayed pulses into a NOR gate.
Your description is not in detail to understand the problem you are facing. So to my understanding, a monostable circuit will have one stable state and after you trigger to a quasi state, it will go to the stable state with some delay. So you can see only one sharp edge. In your case, it is on the leading edge pulse. I think it makes sense. If you need more insight please share you circuit details or the waveforms you see. Good luck.
I think that you want to generate a pulse only on the RISING edge of the signal (Signal transitioning from 0 to 1).
To generate this "Mono-Stable" output pulse (P) you generate a delayed signal (dS) of your Signal (S) then you XOR it P = dS xor S.
Here, the delay time will be the with of your Pulse and you will have a pulse on 0-to-1 and 1-to-0 transitions.
If you want the pulse only on the RISING edge, you should AND the S with not(dS) so you will have this P = S and not(dS).
So , when your Signal just rise and have a ONE value (transition 0-to-1) the delayed is still 0 and you generate the pulse there.
So you only change the XOR for an AND and a NOT. I hope this answer your Question.
If you draw your own gates and want your circuit smaller the implementation should be P = not(S) nor dS.
Best !
@ Joerg Fricke
Thanks for the suggestion of using AND gate with delayed inputs than EXOR gate. But the minimal size AND gate using two NMOS devices would not pass a full Power supply voltage(a perfect logic 1). Hence my reset circuit will not function appropriately. I have already two cascaded CMOS inverters(for buffering purpose) hence all the possibilities of Delayed - positive and negative pulses are readily available. But if I use PMOS instead of NMOS with delayed negative going pulses the reset pulse is not narrow at the rising edge of the Input. Looks like a Two device (NMOS+PMOS) EXOR gate does the job, with shortened trailing edge pulse and a narrow Leading edge pulse widt of ~20ps with 45nm MOS devices.