Normally we will perform both STA and DTA at GLN level. However, in general, STA is preferred in the back-end process. Is it necessary to do DTA again after completing the routing process.
It is impractical to perform dynamic timing analysis of modern-day chips at the chip-level. The industry has moved on to STA at chip-level many years ago.
STA is faster compared to DTA. But DTA simulation is more detail and can give higher accuracy. Some designers prefer finalized their critical paths using DTA.
Personally i would not perform DTA on P&R netlist if gate level netlist is already verified. STA is enough for evaluating the timing performance. But there is one thing i want to note. Todays functional verification concept is quite different compared to past decade. We are talking about UVM, OVM, VMM. I would recommend you to review your functional verification procedures in terms of those new concepts.
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