Due to the design complexity and integration density of the device components, interconnect centric layout design has become an inevitable part to the physical design engineers. Increase in integration density as well as faster switching induces more power consumption i.e. power density resulting need for faster heat dissipation. Generation of heat increases temperature affecting reliability of the chip as an effect of electromigration. In what other ways the chip design gets affected in this scenario due to thermal effects?
Subthrehold current increases,Electrostatic discharge takes place due to increase in temperature. As resistance increases with temp so RC delay of the ckt also increases.
Other effects are:
Threshold voltage and Leakage Current at time 0 as well as with the aging mechanisms such as you mentioned electromigration i.e. one of the biggest challenge in Reliability physics degradation factor of ICs. Please have a look on IEEE IRPS, IEEE IIRW and IEEE IEDM conference proceedings for few good papers about it.
We have reduce the switching activity, also isolation technique can be used
@Ritika Thanks for your answer. Could you please provide some good supporting literature? You may please inbox me.
Thanks @Sivanantham. Am primarily concerned about the effects during routing though.
If you want to know more on Transistor heat creation and transportation, you should read: Heat Generation and Transport in Nonometer-Scale Transistors.
Eric Pop, Sanjiv Sinha and Kenneth E.Gordson; Proceedings IEEE vol. 94, No. 8, August 2006
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