Dear Srinivasan,

As , I understand your question  if you applied Vgs greater than the threshold voltage of MOSFET (In this case 10V shown in the figure) it will conducting . That is why, Vds ringing in your simulation.  My suggestion is kindly reduce the value of Vgs and repeat the simulation may be you will get accurate result.

Thanks

Dear Srinivasan.

I think that you must increase a little the imput voltage to start your test of the converter. some unexpected behaviors can appear testing without imput power suplí.

Are you sure that your converter operates in continuous conduction mode? I think that you should revise this aspect because the waveform in the oscilloscope capture seems be related with operation in discontinuous conduction mode. The posible reasons: high load resistance, low input voltage or low switching frequency.

Thank you Prof. Pawan sir.

Thank you  Prof. Lopez sir. 

Thanks

Stay in touch

Hello Raghavendran,

This is due to the MOSFET capacitances, Cgd and Cds. They are charged/discharged due to the gate pulse and ring with the output inductor (based on the resonance frequency).

Regards,

Michalis Florides.

I agree with Michalis Florides: most like the effect you are observing comes from VGS coupling to the drain via CGD. Though you did not supply the schematics, the oscillation might be influenced by your inductor and load capacitor.

I also agree with Michalis Florides and U. Dreher.  The turn-off gate drive drives the FET drain negative through Cgd, which may well be clamped to 500 mV by the FET body-drain diode.  This voltage then begins to "ring down" through th 1 mH inductance and the sum of Cdg, Cds, the parasitic capacitanc of the inductor and other parasitic circuit capacitances.

Thank you Mr. Michalis Florides

Thank you Mr.U. Dreher

Thank you Mr.Bruce Carsten

sure Prof. Pawan sir. thank you