I don't think there are any good publicly-available models for 32nm FinFETs. Additionally Intel introduced the FinFET at 22nm node and the rest of the foundries followed at 14nm. Hence, I think it makes sense to use a more advanced technology node for your study. We did create 20nm  through 7nm FinFET models and they can be downloaded at ptm.asu.edu. The models are set up for HSPICE simulations, though they can be modified to work with Cadence Spectre as well.

Recently, we developed a 7nm process design kit called ASAP7, which includes all the technology files (Cadence Virtuoso) as well as transistor models for a 7nm FinFET node. You can download the PDK from http://asap.asu.edu. The restriction being you should be affiliated to an academic institution.

Hope that helps.

Regards,

Saurabh Sinha

thank you sir

you can used many models available on line at PTM

@ Saurabh Sinha

Do you have any design kit (FinFET) for Agilent ADS software?

no , sir , i am working in cadence virtuoso and assura... but you can  use ptm models (which are aviable on ptm )   with hspice .. but i still have issue with libraries.

Jagdeep Kaur Sahani can you please explain how to use PTM-MG model using cadence virtuoso tool or spice tool?

just procedure.

FOR PTM-HP procedure taken by me is

1. NMOS4/PMOS4 taken from analog library, then device name, length width according to model library.

2. model library added (ADE-L) then simulation

but what should be procedure for PTM-MG (multigate model) please explain .

u can design circuit in tanner tool using spice ....generate the .sp file from t-spice. change mosfet models and using ptm models and create new netlist with current model files (say 14 nm) . give this net-list in hpsice simulator (not in tanner simulator). download hpsice and chipscope (freely available on net ) for simulation and waveforms.

Does HSPICE freely available? Please give the download link....