Looks like an issue with the transistor templates, it can't find the right pins to make the connections.

what should i do ? @Samual Pagliarini

Hey Hagar!

You can check with cadence support!

The link is attached below : https://community.cadence.com/cadence_technology_forums/f

Do you include cellmap？

Maybe the calview.cellmap file in the directory is the original simple one, and you need to find a correct one in the PDK directory to replace it.

For example a correct one may look like this:

You are missing the calview.cellmap which should be provided in the PDK and it should be linked in calibre to map the extracted devices pins to the design kit devices pins