This is a poly enclosure error. Without actual layout, it's impossible to say what is wrong.
According to design rule - your output terminals can not be touched while designing a semiconductor layout. If the blue and red colors represents two different terminals then it should not be overlapped in the opening terminal.
Blue and red are not terminals, they are layers. The problem arises from the enclosure of the green squares (which I assume are the vias). The enclosure of the bottom one is too close to the left one. The error description should give you a hint of what is the minimum allowed distance, if not you can keep spacing it out until it becomes valid.
kindly i need to make layout for transmission gate but my problem how to put via correctly without an error
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