I am designing a ladder based dac, but I am unable to obtain the correct spectrum plot. I have attached the required images of the obtained output and the spectrum plot. Currently , I have simulated it in a smaller level for analysis purpose at 3bit resolution but I want to design it at 12bit resolution. Kindly help where am I going wrong?
Hi Nupur Pandey ,
the spectrum looks fine to me:
Your signal has a DC component of about -30 mV, so the first peak in the spectrum is at 0 Hz.
The period is 800 ns and obviously contains a lot of harmonics, so the rest of the spectrum consists of the basic frequency 1.25 MHz and integer multiples of 1.25 MHz.
If you increase the resolution and, instead of just cyclically counting, approximate a sinus, then the harmonics will become weaker; and if you add a suitable low pass filter the harmonics will virtually disappear.
As a first step with only 3 bit, you could alternately count up and down, i. e. 0 .. 7, 7 .. 0 etc. The harmonics will become weaker, and could be decreased further with a low pass filter.
What kind of spectrum did you expect?
Nupur Pandey , in the time domain, that corresponds to a pure sinus (or cosinus) signal of 500 Hz (plus some white noise). No similarities to your staircase signal.
As mentioned in my first answer, with a higher resolution (e. g. 12 bit), an approximation to sinus of low frequency, and a low pass filter you will come close to your goal.
Write a short program in C (or your preferred language) which generates an ASCII file with the values of one sinus period in, say, 256 or 1024 steps, multiplied by 2048 (for 12 bit) plus a constant of 2047, and rounded to integer values.
Feed this table of values into your DAC instead of counting. Without filtering, in the time domain you should see a sinus plus very little steps.
Does your last question refer to your first result (3 bit, cyclically counting)? If so, what do you define as signal (continuous (analog) saw tooth or staircase)? And does "very" stand for something like "very poor"?
@Jeorg Fricke I got very poor sndr, sfdr as low as 6dB with staircase waveform.
Here I have attached the spectrum plot of ideal adc and dac present in cadence. The resulting enob=0.293bits
Sinad=3.53dB
SFDR= 6.67dB
What mistake am I making?
Vin= 500mV(DC)+500mV(amplitude)+260k(freq)
Vpulse=0-5V (400nS period)
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