Hello All,
I am working on HVDC VSC converters in DIgSILENT power factory. I have developed the grid and the DSL models of generators, controls and the VSC converters. But, when I run the simulation, it says something on inner-loop iteration reached for some models. I want to know how to resolve this error in DIgSILENT power factory. I have asked this question in the customer portal, but it didn't help me much. They suggested me what I already knew and have tried. I can send the pfd file if required.
I appreciate your help.
Thank You
Anand Prakasha