how to solve this error in VHDL code?

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Aparna Sathya Murthy

Check for :

Timing constraints

UCF for mapping the signal to pin (because the XST synthesis is ok )

Abdelhalim Zekry

Please connect with Dr. Reem. You know her. She is an expert in VHDL and its implementation on FPGA.

Best wishes

Imad A. Shaheen

thanks to all

I have found the solution for the problem after 14 days search for it

It was a license issue because i have last version of VHDL simulation(2017 version) and it need full license to implemented new technology like 5G .

Finally i have get

thanks thanks