I am trying to simulate following the instructions in the pdf attached. But I keep getting the following error:
"Missing or corrupt .oa file in cellview 'cnt/nCNT/spectre cmos_sch cmos.sch schematic veriloga'. The OSS netlister can only process cellviews that have a valid .oa file. This file can be created by either importing the cellview using tools like 'Verilog In' or 'VHDL IN', or by opening and writing the text file in the Library Manager."
How do I solve the problem?
Sundara Siva Kumar v
Verilog file can be imported by using the option,i.e. into Cadence, you can go in the CIW window (Cadence) and then go to File -> Import -> Verilog.
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S M Ishraqul Huq
Dear Mr. Semiu A. Olowogemo
Thank you so much for your reply. It works perfectly.
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