To measure the effect of process variation, I assumed a 10% variation in the threshold voltage of each transistor (each has independent guassian distribution with three sigma value as 0.1*Vth) in a ring Oscillator.
However the reviewer mentioned that this is only the indirect modelling of process variation and I should do a detailed simulation. But I am unable to find out the difference between the direct and indirect modelling of process variation.
Is direct modelling implies that I should consider both local and global variation (say 10% Inter and Intra-die variation in threshold voltage, Oxide thickness and gate length)?
You should use a foundry -supplied library of models. Such libraries usually provide a Monte-Carlo model that includes both intra-, and inter-die variations.
The detailed statistical model of CMOS circuits yield based on process variations was described in my (and my co-authors) article in 1992. See the abstract and reference below. The full text article can be seen through my RG profile's 'Contributions' section.
Article: Prediction of Product Yield Distributions from Wafer Parametric Measurements of CMOS Circuits Leonid Mizrukhin · J. Heuy · Sunil Mehta
ABSTRACT: A technique for predicting the yield distribution of CMOS circuits based on electrical parameter distributions is presented. This technique uses the mean and standard deviation of the measured threshold voltage and mobility of NMOS and PMOS transistors to project the yield of the circuit in a specified design window. The method of prediction is based on a probability model employing the bivariate normal distribution of the transistor parameters. The predicted yield is shown to be very sensitive to the design window specified by the circuit designer for proper functionality. The method thus provides a quantitative means of carrying out tradeoffs between design windows and final product yield.
Full-text available · Article · June 1992 · IEEE Transactions on Semiconductor Manufacturing
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