The leakage power is determined when the transistors are kept in the off sate.

So, you need only to control the transistors in the off state measure the leaksge current and multiply it by the the VDD that is the leakage power =VDD Il where Il is the leakage current of the circuit.

As an example say you have an inverter, then you apply zero voltage on the input of the CMOS inverter the NMOS transistor will be off while the PMOS transistor will be on. So the current is limited by the leakage current by the NMOS transistor to the ground.

In this way one can calculate the leakage off power.

In case of 2 input AND gate you need only to apply zero voltage on the two inputs and see how large is the current drawn from the power supply VDD.

Also the Pl = leakage power = VDD Il with Il the current drawn by the circuit when it is off from the power supply VDD.

Best wishes

The way to measure is trivial, you literally just need one measure statement for the current on the VDD node (let's ignore bulk for now). It doesn't matter what technology node you are using. Check hspice documentation, you are looking for the the .measure() command.

The setup can be more labour intensive, however. For a large circuit with many inputs, you need to make sure you measure leakage for all different input scenarios. This is how standard cell characterization is done, you get one leakage value per input combination per corner.

Hello Prof. Zekri, Prof. Pagliarini and Mr. Ahmad,

Thank you so much for your response and the time you spent.

Best regards

easy, just provide all the supply by single source, should be noted no transition activity happen, by Dc analysis you can get power consumption.